1. Field of the Invention
The present invention relates to an evaluation chip (hereafter “EVA chip”) that is an integrated circuit for program development for a microcomputer used in an emulator, for example. The present invention relates especially to EVA chips in which an interrupt priority order of instruction execution can be freely changed.
2. Background Information
A conventional EVA chip is disclosed in JP H5-151014A, for example. JP H5-151014A discloses an EVA chip that evaluates a program stored in an external program memory and incorporates a central processing unit (hereafter “CPU”) portion and a data latch portion, for example. In this kind of EVA chip, instructions fetched from the program memory are decoded and the decoded results are executed by the CPU portion. After the instruction execution results are temporarily retained in the data latch portion, the results are selectively output to the outside of the chip. The data are evaluated by an externally provided trace circuit, for example.
In the EVA chip disclosed in JP H5-151014A, an interrupt circuit is provided in the chip if interrupt processes are executed by a plurality of interrupt request signals that is applied from outside to the program stored in the program memory. When a plurality of interrupt request signals is applied from outside, the interrupt circuit generates a plurality of interrupt signals in accordance to a predetermined interrupt priority order, encodes the signals to generate interrupt vector addresses, and executes the interrupt processes with the interrupt vector addresses in the CPU portion. Here, the interrupt priority order is predetermined because the interrupt priority order is determined by the specification, so that the configuration of the interrupt circuit can be simplified by fixing the priority order.
However, EVA chips incorporating the conventional interrupt circuit were disadvantageous and inconvenient in that when the priority order specification in the interrupt portion of the internal CPU portion is changed or the priority order specification is different in the interrupt portion of the CPU portion of a series product, the EVA chips cannot be used because the interrupt priority that is featured in the EVA chip is fixed.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved evaluation chip. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.